1. Field of the Invention
The present invention relates to a semiconductor memory device and a data processing system, and more particularly relates to a semiconductor memory device that needs a refresh operation to maintain data stored therein and a data processing system including the semiconductor memory device.
2. Description of Related Art
A memory cell of a DRAM (Dynamic Random Access Memory), which is one of the representative semiconductor memory devices, has excellent characteristics of having a small occupation area per memory cell and achieving a high degree of integration, because it is configured with one transistor and one capacitor. On the other hand, because data written in the memory cell is lost with a lapse of a predetermined time, it is necessary to perform a refresh operation in a periodic manner to maintain the data.
In the refresh operation, a relatively large current flows because it is required to simultaneously activate a plurality of sense amplifiers. Taking this point into consideration, Japanese Patent Application Laid-open No. 2000-30439 proposes a method for controlling a peak current by shifting a timing for performing the refresh operation for each bank, when a refresh command is issued from outside. This method can be easily implemented by providing a transfer path of a refresh signal for each bank in a separate manner in a chip.
Meanwhile, in recent years, there has been proposed a method for configuring a semiconductor memory device, in which a front end part and a back end part of a DRAM are respectively integrated in separate chips and the chips are laminated (see Japanese Patent Application Laid-open No. 2007-157266). According to this method, because an occupation area where a memory core can be assigned is increased in a plurality of core chips in which the back end portions are respectively integrated, it is possible to increase a memory capacity per chip (per core chip). Besides, because the front end parts are integrated, and an interface chip that is common to a plurality of core chips can be manufactured by a process different from that for the memory core, it is possible to form a circuit with a high speed transistor. Furthermore, because a plurality of core chips can be assigned to one interface chip, it is possible to provide a high capacity and high speed semiconductor memory device as a whole.
In this type of semiconductor memory device, from a viewpoint of cost reduction, it is very important to manufacture core chips with the same mask.
However, when core chips are manufactured with the same mask, each of the core chips will have the same circuit configuration, which results in a situation that it is difficult for an interface chip to send a signal to a specific core chip in a selective manner. Therefore, in this type of semiconductor memory device, it is difficult to perform a refresh operation in a selective manner by providing a plurality of transfer paths for a refresh signal as in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2000-30439.